News - FPGA

OpenSPARC for Low Power Next Gen Embedded Designs

posted Sep 14, 2010 11:09 PM by Ashish Banerjee [ updated Sep 14, 2010 11:19 PM ]

Two students of Amity Univ., Rudraksh & Arjun, completed a summer project to study the feasibility of modifying OpenSPARC for next generation low power embedded applications. The project was supervised by Prof. Anshul Kumar of IIT Delhi. I have attached the report below.

| Attachments: SPARC Summer Report _Arjun & Rudraksh_.pdf

Open PDK 1.0 Released

posted Mar 14, 2010 6:01 AM by Ashish Banerjee [ updated Mar 14, 2010 6:03 AM ]

Silicon fabrication industry consortium has release an Open Standards for inter-operable PDK (Process Design Kit), under the banner of si2.org (Silicon Integration Initiative). PDK are the building blocks of Standard Cell Libraries.

http://i.cmpnet.com/eetimes/news/online/2010/03/TSMC_SpringSoftWPMarch4.pdf (1.9MB)

Altera 28nm FPGA

posted Feb 4, 2010 8:07 PM by Ashish Banerjee

Altera has announced its 28nm FPGA/ASIC technology. What I am excited about this technology is that its PIN compatibility between the HardCopy (Hybrid of ASIC and FPGA) and its Spartan FPGA chips. This will allow successful designs to be reproduced in volumes at low cost. Also, it has a few killer hard IP built in. Check out Altera announcement :

http://www.altera.com/b/innovating-at-28-nm.html

FPGA	Search this site