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JaM : FPGA synthesizable Native Java Machine

 JaM is an idea for an experimental FPGA synthesizable processor that executes Java Opcodes natively. Its design will be derived solely from the OpenSPARC source code base. 

JaM comes in two flavors, Tarbooz ( तरबूज ) and Anar (अनार). 

JaM Tarbooz is for server side Java application (Java EE) and JaM Anar is for Smartphone (or Java SE) application. The JVM instruction set for both the cases are the same, only the implementation related to number of hardware threads, processor cores and processing powers changes.   

The challenge here are two folds. First is to maximize the common source code, so as to minimize the code maintenance.
The second challenge is to create two design sets. One for JaM Anar, that is optimized for Low Power and Low Logic counts, fitting into say Actel's Igloo Nano family; Second, for JaM Tarbooz, that is a high performance multi-core and CMT (Chip Multi Threaded) suitable for high bandwidth processing for telecom network back-end infrastructure. It should be implementable in high performance FPGA like recently announced Altera's 28nm HardCopy/Stratix and Xilinx Virtex series.      

FPGA are good for experimentation in processor designs, and if proven successful, they get to be synthesized into silicon as real Hard Core IP.  

The Java VM Specification can be found here:

JaM : Tarbooz

 Jam Tarbooz is intended to be the XXL size of the de-virtualized Java Machine.
Thus from the implementation perspective we shall visualize it as at the same level as an OpenSPARC single processor core (spc).
The module input and output signals will be same as spc. 

We shall begin by copying the spc.v module to jam_tz.v file, as a starting point.

The design idea for doing so is to ensure that the Java Machine core should be able to exist within a multi-core OpenSPARC derivative along with the unmodified core, spc. Thus extending the OpenSPARC design by making it a hybrid core CMT.

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