Digging Into The OpenSPARC Source Code

 OpenSPARC is an Open Source 64 bits RISC processor, its current T2 version is a FPGA synthesizable single core derived from UltraSPARC T2, which has 8 cores with total of 64 hardware threads per processor. The OpenSPARC T2 source code has provisions for CMP (Chip Multi-Processor) thus enabling multiple cores with multiple hardware threads (HMT) thus making it a true CMT (Chip Multi-Threading) Open Source design. The T2 design is capable of 64 hardware threads.

A Question in need of an answer:
  What does it take to double the number of threads per core and double the cores per processor?
That is, 16 threads per core and 16 cores per processor, total of 256 threads. Shall we call this T4 ? Can it be implemented in 28 nm process?

A Brief SPARC History

As per the OpenSPARC Internals book (pg 33, sec
The UltraSPARC Architecture architecture is derived from the SPARC
architecture, which was formulated at Sun Microsystems in 1984 through
1987. The SPARC architecture is, in turn, based on the RISC I and II designs
engineered at the University of California at Berkeley from 1980 through
1982. The SPARC “register window” architecture, pioneered in the UC
Berkeley designs...

The OpenSPARC source code was derived from UltraSPARC design.
There are two versions of UltraSPARC T1 and T2. T1 is the older version having 4 hardware threads per core and 8 cores per processor. T1 was released in open source around March 2006. A subset of T2 was open sourced in first quarter of 2008 and the original UltraSPARC T2 contains 8 hardware threads per core and 8 cores per processor that is 64 threads in total. 

Why Dig into the Source?

Why people gawk at a work of art? or read a poem? The answer to these three questions may differ from person to person, but my take is that connoisseurs love excellence and love to appreciate when they come across one. 

A more down to earth reason may be to learn programming the circuits from a real life processor, in use in commercial and extreme computing environment. Also OpenSPARC is FPGA synthesizable, and thus one can create subsets or a specialized version of it.

To "Use the Force" (with apologies to Star Wars, the movie) , one needs to RTSL. 

RTSL: Read The Source Luke

Before you begin to RTSL, you need to download the source (I have used the 1.3 release ) from the OpenSPARC.net site, and also read the OpenPARC Internals book.  

Though the OpenSPARC Internals book will get you started, to actually understand the RTL codes, you will need to refer to the Micro Architecture Reference manuals found in the doc sub-directory of the source code. 

Needless to say, you must be familiar with Verilog. If not, then you should read a few tutorials. Mainly focus on Synchronous versus Asynchronous designs; keywords like <= , = and assign .  Keep in mind that '=' assigns sequentially while '<=' is a parallel assignment construct.

OpenSPARC T2 FPGA Source Layout

FPGA synthesis of a microprocessor is mainly useful for studying and understanding the processor designs and architectural experimentation.
The FPGA related source code can be found at: (note: $home is the location where you have unzipped the OpenSPARC T2 source code, OpenSPARCT2.1.3.tar.bz2)

The file, $home/OpenSPARC/design/fpga/rtl/fpga_rtl.flist  contains a list of all Verilog (.v) source files being used for synthesizing OpenSPARC T2 processor. 

T2 Top Level:

The T2 Module, calls other modules like spc (Single Processor Core), ccx (cross bar switch between cores and L2 cache) and a bridge to the  wishbone interconnect protocol (spc2wbm)

The OpenSPARC T2 CMT (Chip Multi-Threaded) Option

Though, the FPGA design for T2 uses single core, there is a provision to extend the design to CMP (Chip Multi-Processor).
The cpu.v file ( $home/OpenSPARC/design/iop/cpu/cpu.v ) has provision to define multiple processor cores using the `ifdef conditional directives CMP and OPENSPARC_CMP .  

OpenSPARC has big endian address space. That is higher the address significance higher is the significance of the data being addressed. that is a[0] is the LSB (Least significant bit) and a[63] is the MSB (Most Significant Bit).

The views expressed on this blog are my own and do not necessarily reflect the views of my employer.