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| ASI | Address Space Identifier | | |
| ASR | Ancillary State Register | | Also an Opcode mnemonic |
| CAM | Content Addressable Memory | Wiki | |
| CASA | Compare and Swap | | Sparc instruction opcode |
| CMP | Chip Multi-Processor | | (Multicore) Multiple processor Cores glued into a chip |
| CMT | Chip Multithreaded | | CMT = CMP x HMT |
| CPI | Cycles Per Instruction | | |
| CTU | Clock and Test Unit | | Clock generation and JTAG interface |
| DIMM | Dual Inline Memory Module | Wiki | |
| DMA | Direct Memory Access | Wiki | |
| DMU | Data Management Unit | | manages PCI-e data interchange with processor |
| DTLB | Data Translation Lookaside Buffer | | Translates Virtual to Physical Memory. Part of MMU within a processor core |
| ECC | Error Correcting Codes | Wiki | |
| EXU | Execution Unit | | part of T2 core, 2 EXU per core. Each EXU has 4 HMT |
| FBD | Fully buffered DIMM | Wiki | |
| FGU | Floating-point and Graphic Unit | | Part of processor core, T2 has one FGU per core |
| FPU | Floating Point Unit | | also called FGU |
| FRF | Floating-point Register File | | Register File concept not to be confused with Storage File system |
| HWTW | Hardware Table Walk | | part of MMU (within a processor core) |
| IFU | Instruction Fetch Unit | | part of the core, each core has 1 IFU |
| ILP | Instruction Level Parallelism | | |
| IRF | Integer Register File | | Register File concept not to be confused with Storage File system |
| ITLB | Instruction Translation Lookaside Buffer | | Translates Virtual to Physical Memory. Part of MMU within a processor core |
| JBI | J-Bus Interface | | Connect processor to I/O sub systems. Used for DMA |
| JTAG | Joint Test Action Group | Wiki | IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture |
| LMQ | Load Miss Queue | | Part of processor core, see section 5.3.3 of OpenSPARC T2 Core Microarchitecture Specification |
| LRU | Least Recently Used | | |
| LSU | Load Store Unit | | one per processor core |
| MMU | Memory Management Unit | | |
| NRU | Not Recently Used | | cache replacement algorithm |
| NUMA | Nonuniform Memory Access | | |
| PEU | PCI-Express Unit | | |
| PIO | programmed I/O | | |
| PLL | Phase Lock Loop | Wiki | Synchronized clock signal generation |
| PMU | Perfomance Monitor Unit | | see Chapter 15 of OpenSPARC T2 Microarchitecture Specification |
| PPN | Physical Page Number | | PPN is stored in TLB |
| RISC | Reduced Instruction Set Computers | Wiki | |
| RMO | Relaxed Memory Order | Wiki | see Section 5.4.4.2 Block Stores of OpenSPARC T2 Microarchitecture Specification |
| RPN | Real Page Number | | context MMU and Hardware Table Walk |
| RTL | Register Transfer Level | Wiki | |
| SIMD | single instruction, multiple data | Wiki | |
| SMT | simultaneous multithreading | Wiki | also called hardware threads |
| SPU | Stream Processor Unit | | cryptographic accelerator |
| SSI | Serial System Interface | | |
| STB | Storage Buffer | | part of the strand within the Processor Core, see Section 5.3.4 of OpenSPARC T2 Core Microarchitecture Specification |
| STD | store doubleword integer (mnemonic) | | Sparc Instruction opcode |
| TLB | Translation Lookaside Buffer | | Translates Virtual2Physical Memory, two types are Instruction and Data TLB, Part of MMU within a processor core |
| TLP | Transaction Layer Packet | | |
| TLP | Thread Level Parallelizm | | |
| TLU | Trap Logic Unit | | Part of the Processor Core, handles traps & Interrupts |
| TSB | Translation Storage Buffer | | or Page Table (part of MMU) |
| TTE | Translation Table Entries | | part of MMU |
