OpenSPARC T2 is a FPGA synthesizable single core derived from the UltraSPARC T2, which is a CMT (Chip Multi-Treaded) System-on-Chip (SoC).
A Chip Multi-Threaded (CMT) processor has multi-processor cores and each core capable of simultaneously executing multiple threads in hardware or Hardware Multi-Threading (HMT).
CMT = CMP (Chip Multi-Processing ie. Multi-core) x HMT (Hardware Multi-Threading)
The UltraSPARC T2 has 64 threads (CMT) = 8 cores (CMP) x 8 threads (HMT) per core.
UltraSPARC T2 has 8 cores and each core has a L1 cache of 16 KB of Instruction cache and 8 KB of Data Cache.
The OpenSPARC source code corresponding to the above block diagram is as follows.
The multi-core processor (CMP) top level module can be found in
The cache crossbar top level module is
The memory controller top module is
The System Interface Unit top level is
The L2 (Level 2) Bank module is
The physical layout within the Silicon Real Estate of UltraSPARC T2 (from which the OpenSPARC T2 is derived) is shown below.
OpenSPARC T2 has a single core, a cache crossbar interconnect (ccx) and a few OpenCores.org derived components like Wishbone Memory Controller.